06 Aug
|
Leading
|
Bengaluru
Position
Overview
We are seeking
a highly motivated IP/SoC Design Verification Engineer with strong expertise in
functional verification methodologies and SoC/IP validation. The ideal
candidate will be responsible for verifying complex ASIC/SoC designs and
ensuring first -time -right silicon quality for next -generation semiconductor
products.
The role requires
deep understanding of SystemVerilog, UVM -based verification environments,
protocol verification, and debugging across IP and SoC -level verification
flows.
Key
Responsibilities
- Develop and execute verification plans for both
IP and SoC -level designs.
- Build reusable verification environments using
SystemVerilog and UVM methodology.
- Develop test benches, assertions, checkers, coverage
models, and test cases.
- Perform functional, regression, and coverage -driven
verification.
- Debug RTL and verification environment issues to
identify root causes.
- Collaborate closely with RTL Design, Architecture,
Firmware, and Validation teams.
- Participate in design reviews and verification
closure activities.
- Ensure verification quality through functional and
code coverage metrics.
- Work on protocol and subsystem verification for
complex SoC designs.