We Are At Synopsys we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence from self-driving cars to learning machines We lead in chip design verification and IP integration empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation You Are You are a passionate ASIC Digital Design expert with a robust foundation in micro-architecture and RTL coding eager to make a mark on the next generation of high-speed interface IP You thrive in a collaborative environment where your deep technical acumen and hands-on experience allow you to tackle complex design challenges Your commitment to quality and innovation is evident in your meticulous approach to design validation and problem-solving You are hungry for opportunities to learn guide others and deliver results that exceed expectations What You ll Be Doing Understanding and analyzing complex IP specifications to translate requirements into robust micro-architectures Defining and developing high-quality RTL code using Verilog SystemVerilog for High-Speed SERDES PHY IP blocks Collaborating with cross-functional teams including architecture verification and backend to resolve issues creatively and efficiently Supporting the verification team by helping debug and resolve complex functional issues Running and interpreting results from ASIC development tools including Lint CDC and RDC and driving the creation of waivers as needed Guiding and mentoring junior engineers sharing best practices and technical know-how to elevate team performance Participating in design reviews and contributing to continuous improvement of design methodologies and flows The Impact You Will Have Accelerate the development of industry-leading SERDES PHY IP that powers high-performance next-generation SoCs Drive innovation in digital design contributing to the high quality reliability and performance that Synopsys customers expect Facilitate smooth cross-team collaboration ensuring efficient issue resolution and timely project delivery Enhance the verification and validation process by proactively identifying and addressing design and integration challenges Support the adoption of best-in-class design methodologies improving productivity and reducing time-to-market for customers Mentor and develop junior team members fostering a culture of technical excellence and continuous learning What You ll Need Bachelor s or Master s degree in Electrical Electronics Engineering or related field 8 -12 years of hands-on experience in ASIC digital design micro-architecture and RTL coding Expertise in Verilog SystemVerilog and familiarity with VHDL Proficiency with high-speed interface protocols PCIe Ethernet etc Experience with ASIC development tools Lint CDC RDC Synthesis Static Timing Analysis STA and Formal Verification Understanding of RTL to GDSII flow and backend considerations Familiarity with scripting languages such as Shell or Perl for automation and flow development Who You Are Detail-oriented and committed to delivering high-quality results Proactive problem solver with a collaborative and innovative mindset Excellent communicator able to articulate technical concepts to diverse audiences Adaptable and quick to learn emerging technologies and methodologies Natural mentor and team player willing to share knowledge and support colleagues The Team You ll Be A Part Of You will join a world-class team focused on the development of high-speed SERDES PHY IP collaborating with experts in architecture verification and silicon implementation This dynamic cutting-edge group values knowledge sharing technical rigor and a growth mindset working together to deliver industry-leading solutions that enable Synopsys customers to realize their most ambitious designs Rewards and Benefits We offer a comprehensive range of health wellness and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process

📌 Asic Digital Design, Sr Staff Engineer - Serdes Ip Rtl Design (Telangana)
🏢 Synopsys
📍 Telangana