This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time

Roles & Responsibilities

- Perform block-level and full-chip Static Timing Analysis (STA).
- Drive timing closure across all timing modes and corners.
- Analyze and resolve setup and hold violations.
- Work closely with Physical Design teams for timing optimization.
- Generate and review timing constraints (SDC).
- Perform timing signoff checks, including noise and variation analysis.
- Debug timing issues and provide timing ECO solutions.
- Collaborate with RTL, Synthesis, DFT, and Physical Design teams.
- Ensure timing closure at advanced technology nodes.

Required Skills

- Strong hands-on experience in STA and timing signoff.
- Expertise in setup/hold analysis, timing closure, and ECO implementation.
- Experience with MMMC concepts and timing constraints development.




- Good understanding of synthesis, floorplanning, placement, CTS, routing, and signoff flows.
- Knowledge of SI, Crosstalk, OCV/AOCV/POCV concepts.
- Experience with industry-standard tools such as:

o Synopsys PrimeTime o PrimeTime SI o ICC2 (Good to have)

o Tempus (Valuable to have)

- Strong debugging and problem-solving skills.
- Excellent communication and stakeholder management skills.

Preferred

Qualifications

- Experience working on advanced technology nodes (7nm/5nm/3nm preferred).
- Exposure to full-chip timing closure and tape-out activities.
- Experience handling customer interactions and technical reviews.

Good-to-have skills

Cadence

📌 STA Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru