Sr. DFT Engineer

Experience: Not Available to Not Available years

Location: Noida

Skills: DFT architecture, scan, ATPG, MBIST, boundary scan, scan insertion, chain stitching, compression techniques, fault coverage, DFT-related issues, RTL, Physical Design, STA, pattern validation, gate-level simulations, silicon bring-up

Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with solid expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and quality silicon.

Key Responsibilities

- Define and implement DFT architecture including scan, MBIST, and boundary scan.
- Perform scan insertion, chain stitching, and compression techniques.
- Generate and analyze ATPG patterns to achieve high fault coverage.
- Debug and resolve DFT-related issues across design and silicon stages.
- Work closely with RTL, Physical Design, and STA teams for smooth integration.
- Support pattern validation, gate-level simulations, and silicon bring-up.
- Ensure compliance with DFT and testability requirements.

More information about NXP in India...

📌 Sr. DFT Engineer (India)
🏢 NXP Semiconductors
📍 India