Senior RTL Design Lead

Experience: 5 to 7 years

Location: Bangalore, India

Skills: RTL Design, Verilog, VHDL, Digital Design Principles, Modelsim, Synopsys Design Compiler, Design Verification, UVM, Systemverilog

Job Summary

Candidates with 5 to 7 years experience is mandatory

Experience in Full chip RTL integration is preferred

Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc.

Experience in RTL Synthesis

Scripting experience

Experience integrating IP's like PCIe, USB, Ethernet etc.

Should be able to lead a team of 2 to 3 Entry Level engineers

Key Responsibilities

1.

Utilize Advanced Rtl Design Techniques And

Tools, Such As Verilog And Vhdl, To Create Effective And Optimized Hardware Designs That Align With User Requirements And Business Goals.

2.

Lead And

Mentor A Team Of Rtl Designers,



Providing Technical Guidance And Ensuring The Successful Delivery Of High-Quality Design Solutions That Adhere To Project Timelines And Specifications.

3.

Present And Articulate Design

Concepts, Strategies, And Solutions To Stakeholders, Playing A Pivotal Role In Shaping The Overall Design Vision And Ensuring Alignment With Organizational Objectives.

4.

Conduct Regular Reviews Of Design Processes

And Methodologies, Integrating Industry Trends And Emerging Technologies To Drive Innovation And Enhance Design Excellence.

Skill Requirements

1.

Advanced Proficiency In Rtl Design Using

Verilog And Vhdl.

2.

Solid Knowledge Of Digital Design Principles

And Methodologies.

3.

Familiarity With Simulation Tools Such As

Modelsim And Synthesis Tools Like Synopsys Design Compiler.

- Strong Understanding Of Design Verification Processes And Tools, Including Uvm And Systemverilog.

Other Requirements

1.

Certification In Rtl Design Or Equivalent (Optional But Valuable).

📌 Senior RTL Design Lead (India)
🏢 HCL Technologies
📍 India