? We are Hiring: Design Verification Engineers (CPU/GPU IP & ASIC) ? ACL Digital is looking for DV Engineers with 2–4 years of experience to drive functional verification for complex CPU/GPU ASICs and IP cores in Hyderabad! If you have solid hands-on experience in C/C++, SystemVerilog, DPI/PLI, and advanced debugging using Verdi, VCS, GDB, or Valgrind, we want to hear from you. You’ll be responsible for developing constrained-random/directed test plans, assertion-based verification, and executing simulation runs under aggressive, high-performance timelines.
Immediate joiners or candidates with a 0–30 day notice period are preferred.