? We're Hiring: Design Verification Engineers (SystemVerilog/UVM | RNM | Memory Modeling) We're looking for experienced Design Verification Engineers to join an exciting project focused on building high-fidelity memory models around actual memory arrays using SystemVerilog/UVM. If you have a strong background in Design Verification (DV), Real Number Modeling (RNM/Wreal), and memory architecture, we'd love to hear from you.
Experience: 5+ Years ? Key Responsibilities Develop and verify memory models around real memory arrays using SystemVerilog/UVM.
Build and maintain Real Number Models (RNM/Wreal) for mixed-signal verification environments.
Understand and model complex memory array topologies to achieve accurate behavioral representation.
Work closely with RTL, design, and verification teams to ensure robust functional verification.
Debug and optimize verification environments using industry-standard simulation and debug tools.
Collaborate across teams to improve verification methodologies and model accuracy. ✅ Required Skills 5+ years of hands-on experience in Design Verification (DV).
Robust expertise in SystemVerilog and UVM.
Proven experience with Wreal/Real Number Modeling (RNM).
Good understanding of standard DV methodologies, RTL, verification flows, and testbench development.
Strong knowledge of memory array topologies (mandatory).
Exposure to Non-Volatile Memory (NVM/NVMe) technologies is a strong advantage.
Experience with Cadence Xcelium and SimVision simulation/debug environments. ⭐ Nice to Have Ability to review and understand circuit implementations in Cadence Virtuoso.
Exposure to mixed-signal verification methodologies. ? Who Should Apply? This role is ideal for engineers who enjoy solving complex verification challenges, building accurate memory models, and working at the intersection of digital verification and memory architecture.