Key Responsibilities

•

Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.

•

Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.

•

Perform detailed transistor-level and block-level layout implementation for high-speed circuits.

•

Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.

•

Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.

•

Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.

•

Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.

•

Ensure layouts comply with all foundry-specific design rules and reliability requirements.

•

Generate extracted netlists for post-layout simulations and back-annotation activities.

•

Work closely with Design Engineers (DEs) to support post-layout verification and performance closure.

•

Document layout methodologies, notes, and implementation details in block review documents.

•

Participate in design reviews and implement corrective actions resulting from layout reviews.

•

Optimize layout for area, matching, parasitics, signal integrity, electromigration (EM), and manufacturability.

Required Qualifications

•

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.

•

Strong experience in 7nm FinFET technology node layout development.

•

Proven expertise in high-speed analog and mixed-signal layout design.

•

Hands-on experience with advanced node layout challenges including:

o

Multi-patterning awareness o

Device matching o

Parasitic optimization o





Reliability rules cyient.com

2

•

Strong understanding of

o

DRC o

LVS o

Parasitic extraction (PEX)

o

ERC checks

•

Experience generating extracted netlists and supporting post-layout simulations.

•

Excellent understanding of analog layout techniques:

o

Common centroid o

Interdigitation o

Symmetry o

Matching o

Shielding o

Guard rings

•

Ability to read and interpret circuit schematics and design specifications.

Preferred Skills

•

Experience with advanced nodes such as 3nm, 4nm, 5nm, 6nm, 7nm, 10nm, or 12nm FinFET.

•

Experience in layouts for

o

PLLs o

High-speed SerDes o

Clocking circuits o

Data converters (ADC/DAC)

o

High Bandwidth Memory o

RF or mixed-signal IPs

•

Knowledge of EMIR analysis and reliability verification.

•

Familiarity with process variation and layout-dependent effects (LDE).

•

Experience working with global semiconductor customers.

EDA Tools Expertise

Hands-on experience in one or more of the following:

•

Cadence Virtuoso Layout Suite

•

Calibre DRC/LVS/PEX

•

Synopsys IC Validator

•

Custom Compiler

•

Cadence Pegasus

•

Analog Design Workplace (ADE)

Key Competencies

•

Strong attention to detail

•

Layout quality ownership

•

Problem-solving and debugging skills

•

Effective communication with cross-functional teams

•

Ability to handle multiple design blocks simultaneously

•

Commitment to first-pass silicon success

Nice to Have

•

Experience with 5nm/3nm technology nodes.

•

Knowledge of automation or scripting (SKILL, Perl, Python, Tcl).

•

Experience in IP development for high-performance computing, networking, or AI applications.

cyient.com

3

Keywords: Analog Layout, Mixed-Signal Layout, FinFET, 7nm, High-Speed Layout, DRC, LVS, PEX, Floorplanning, Cadence Virtuoso, Calibre, SerDes, PLL, HBM.

📌 Senior Analog Layout Engineer (Bengaluru)
🏢 Cyient
📍 Bengaluru