Are you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.
Required Experience
- 8+ years of overall VLSI/Physical Design experience is preferred.
- 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
- Solid expertise with industry-standard EMIR analysis and sign-off methodologies.
- Excellent debugging, analytical, and cross-functional collaboration skills.
Key Responsibilities
- Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
- Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
- Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
- Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
- Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
- Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.
📌 Lead ASIC PD / EMIR Engineer (Bangalore Metropolitan Area)
🏢 smartsoc solutions
📍 Bangalore Metropolitan Area
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