06 Aug
|
Mirafra
|
Bengaluru
- Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
- Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
- Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories.
- Should possess valuable knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes
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📌 Memory Layout Design Engineer (Bengaluru)
🏢 Mirafra
📍 Bengaluru