- Define high-speed IO architecture for PCIe/Ethernet-224G/448G scale-up fabric/CPO-optics to electrical interfaces

- Define die-to-die interface architecture for UCIe integration: flit formats, credit-based flow control, sideband management, and latency targets

- Architect the SerDes-to-photonics interface, retimer integration, and co-packaged optics (CPO) readiness

- Own the signal integrity budget: TX/RX equalization, channel loss allocation, crosstalk margins, and jitter decomposition across the full channel

- Implementation Oversight

- Guide SerDes PHY selection and evaluation; assess vendor IP (custom vs. licensed), and establish integration requirements

- Define and review UCIe PHY integration: bump map, power domain partitioning, analog/digital co-design requirements, and pad ring architecture

- Collaborate with digital architecture lead on protocol bridge design — PCIe TLP ↔ UCIe flit conversion, flow control, error handling

- Drive DFT and compliance test architecture for PCIe certification and UCIe conformance testing

- Establish PVT margin strategies and power management per-lane DVFS, shutdown sequences, and IVR chiplet coordination

Customer & Ecosystem Engagement

- Serve as primary technical interface to anchor customers and engaging hyperscaler architecture teams (AWS, Google, Microsoft, Meta) to validate product definition against platform requirements

Roadmap & IP

- Contribute to RTL reuse strategy — enabling derivative roadmap SKUs with minimal re-spin





- Identify and scope patentable innovations in UCIe integration, adaptive equalization, and multi-protocol bridge architectures

What We’re Looking For

- 15+ years in high-speed interface architecture; 5+ years at Principal level or higher in a fabless or IDM semiconductor environment

- Deep expertise in PCIe architecture — from PHY layer through controller and protocol stack; direct tape-out experience strongly preferred

- UCIe standard familiarity — flit-based transport, sideband protocol, and die-to-die integration in 2.5D/3D packages

- Signal integrity expertise: S-parameter analysis, channel simulation (HSPICE/IBIS-AMI), eye diagram closure, and crosstalk budgeting

- Experience with advanced nodes and advanced packaging (CoWoS, EMIB, InFO)

- Track record of driving complex multi-party IP integrations from architecture through tape-out

Valuable to Have

- Experience with 224G/400G+ SerDes architectures for scale-up AI fabric (NVLink, UALink, Ultra Ethernet, or proprietary)

- Familiarity with electrical-optical co-design for CPO or near-package optics; EIC retimer or photonic interface experience

- Prior work in chiplet-based multi-die architectures — bumping strategy, KGD handling, heterogeneous integration

- PCIe-SIG membership or active contribution to UCIe Consortium working groups

- Prior startup experience or comfort with early-stage ambiguity and fast-paced execution

Skills: design,phy,architecture

📌 High-Speed IO Architect - Digital (Bengaluru)
🏢 Virtual Connect Solutions
📍 Bengaluru