Field-Programmable Gate Arrays Engineer (Bengaluru)

Field-Programmable Gate Arrays Engineer (Bengaluru)

06 Aug
|
Xeedo Technologies
|
Bengaluru

06 Aug

Xeedo Technologies

Bengaluru

– Senior FPGA Engineer (2–8 Years Experience)

Location: Bengaluru, Karnataka

Experience: 2–8 Years

Employment Type: Full-Time Key Responsibilities Design, develop, and implement FPGA-based solutions for RF, DRFM, and high-speed digital systems.

Develop RTL using Verilog/VHDL and perform FPGA verification.

Execute the complete FPGA development flow including:

RTL Design

IP Integration

Simulation

Synthesis

Place & Route

Timing Closure

Bitstream Generation

Hardware Bring-up and Debugging

Integrate and customize vendor IPs including DDR, Ethernet, PCIe, SPI, I2C, UART, PLL, and SerDes.

Perform FPGA simulation and debugging using QuestaSim/ModelSim or equivalent tools.

Collaborate with RF, Embedded, Hardware, and System Engineering teams during product development.

Support board bring-up,hardware validation, and system integration activities.

Develop and maintainFPGA design documentation and technical reports.

Participate in design reviews, technicaldiscussions, and architecture planning.

Optimize FPGA resource utilization, timing performance, and power consumption.

Required Skills B.E./B.Tech/M.Tech in Electronics, ECE, EEE, or a related discipline.





3–5 years of hands-onFPGA development experience. Strong experience with:

Xilinx Vivado

Intel Quartus Prime

Proficiency in Verilog and/or VHDL.

Strong understanding of FPGA implementation flow.

Experience with FPGA timing constraints and timing closure techniques.

Experience integrating vendor IPs and high-speed interfaces.

Knowledge of DDR, PCIe, Ethernet, SPI, I2C, UART, and high-speed serial communication.

Experience with board-level debuggingand hardware validation.

Valuable understanding of digital design principles and signal processingconcepts.

Preferred Qualifications Experience in Defence, Electronic Warfare (EW), DRFM, Radar, SDR, or Satcom systems.

Experience working on FPGA-basedsignal processing applications.

Familiarity with high-speedtransceivers and SerDes architectures.

Knowledge of TCL scriptingand FPGA design automation.

Experience working with DRDO Labs, Defence PSUs (BEL, HAL, BDL), ISRO, or Defence R&D; programs will be a strong advantage.

Location Bengaluru, Karnataka Immediate Joiners Preferred Please share your profile to [email protected]

📌 Field-Programmable Gate Arrays Engineer (Bengaluru)
🏢 Xeedo Technologies
📍 Bengaluru

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