Design Verification Engineer | 5-7 Years

We are looking for a Design Verification Engineer with 5-7 years of ASIC/SoC verification experience to develop and execute verification environments for complex digital designs. Key Requirements:

Strong experience in SystemVerilog and UVM

Expertise in ASIC/SoC functional verification

Experience building and debugging verification testbenches

Good understanding of digital design concepts and RTL verification

Hands-on experience with simulators such as VCS, Xcelium/Incisive, or Questa/ModelSim

Strong debugging, coverage closure, and problem-solving skills Good to Have:

Experience with AXI/AHB/APB or other industry-standard protocols

Knowledge of SVA, Python, Perl, or Shell scripting Qualification:

Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or a related field Why Join Us?

Work on cutting-edge ASIC/SoC designs

Cooperative engineering environment

Excellent learning and growth opportunities

Competitive compensation and benefits package

📌 Design Verification Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru