Required Technical Qualifications

- Excellent skill in HDLs (Verilog, VHDL, and System Verilog) for writing clean, synthesizable RTL.

- Solid understanding of RTL design fundamentals, microarchitecture, AMBA/AXI bus architecture, pipelining, finite state machines (FSMs), and digital design principles.

- Excellent analytical problem-solving skills and valuable mathematical skills.

- Strong understanding of timing paths, CDC, and Static Timing Analysis (STA).

- Experience in RTL simulation and verification.

- Knowledge of AMD, Intel (Altera), Microchip, and Lattice FPGA/SoC architectures and proficiency with their respective development tools.

- Exposure to AMD Zynq SoCs, ARM processing systems, and AMBA/AXI bus architecture.

- Proficiency in improving speed, power and area efficiency of RTL designs, and integration of IP cores

.

- Experience in standard serial interfaces like I2C, SPI, UART.





- Exposure to high-speed interfaces and controllers such as MIPI CSI/DSI, DDR, PCIe, USB, Ethernet, and LVDS/Sub-LVDS.

- Familiarity with scripting for automation (Tcl , Python) and version control systems (Git).

- Hands-on experience with lab test equipment like logic analyzers, MSO, and on-chip debug.

- Basic knowledge in digital and analog electronics and ability to read circuit schematics.

Desired Qualifications

- Basic understanding in digital image/video processing or hardware DSP pipelines.

- Programming skill in Python, Matlab, C++ etc for software simulation before RTL implementation.

Experience -

3 Years+

Educational Qualitification

- BTech (ECE , EEE), MTech (VLSI)

📌 Design Engineer RTL (Kochi)
🏢 Digital Core Technologies
📍 Kochi