Your Team, Your Impact

The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications.

Job Responsibilities

- Architect and implement simulation test bench in UVM.
- Develop and execute test-plans for verifying correctness and performance of the design.
- Own and debug failures in simulation to root-cause problems
- Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations

What Were Looking For Requirements
- Bachelor s degree in CS/EE with 8+ years of relevant experience, or Master s degree in CS/EE with 6+ years of relevant experience
- Strong background in IP verification, including methodology and testbench development
- Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++
- Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations




- Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus
- Robust analytical and problem-solving skills
- Ability to manage multiple tasks in a fast-paced environment
- Excellent communication, interpersonal, and teamwork skills
- Capable of interfacing effectively at all levels within and outside the organization
- Proactive in participating in problem-solving and quality improvement initiatives
- Experience in working on Processor based Subsystems
- Experience in working on HW Security is desirable

This position may require access to technology and/or software subject to U. S. export control laws and regulations, including the Export Administration Regulations EAR. As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U. S. Department of Commerce and/or the U. S. Department of State. Except for U. S. citizens, lawful permanent residents, or protected individuals as defined by 8 U. S. C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Senior Staff Engineer - Design Verification (Pune)
🏢 Marvell Semiconductors
📍 Pune