We are looking for an experienced DFT Engineer with solid expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and quality silicon.
Key Responsibilities
- Define and implement DFT architecture including scan, MBIST, and boundary scan.
- Perform scan insertion, chain stitching, and compression techniques.
- Generate and analyze ATPG patterns to achieve high fault coverage.
- Debug and resolve DFT-related issues across design and silicon stages.
- Work closely with RTL, Physical Design, and STA teams for smooth integration.
- Support pattern validation, gate-level simulations, and silicon bring-up.
- Ensure compliance with DFT and testability requirements.
More information about NXP in India...
#LI-2734
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Sr. DFT Engineer (Noida)
🏢 Kinara.ai
📍 Noida
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.