Develop constrained-random UVM testbenches from scratch for recent IP blocks
Write SystemVerilog Assertions (SVA) for protocol checking &property; verification
Work with RTL designers to resolve verification
Set up & automate regression runs; triage fail
Required Candidate profile
3-7 Exp UVM verification Engineer medical SOC projects
Must have UVM / OVM methodology SystemVerilog class-based, SVA assertion
Functional coverage closure Python / Perl scripting
Synopsys VCS, Questa