- As part of the AECG integration team, the candidate will be involved in different phases of Tile/block Physical implementation starting from RTL to final GDSII.
Job Requirements:
- Master s/bachelors degree in electrical/ Electronics engineering with 4 to 8 years of experience in semi-custom or PNR design
- Expertise in physical implementation of digital blocks using industry standard Palace and Route (PnR) Tools meeting PPA spec
- Expertise in floor planning including power grid design to meet EMIR specifications
- Excellent understanding of timing concepts and signoff
- Hands on experience in Generating and Implementing ECOs to fix timing, noise and EMIR violations
- Good hands on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool
- Participate and contribute in enhancing physical design methodologies and flows
- Excellent scripting skills in tcl/ perl and scripting savvy
- A good understanding of electrical, timing and reliability issues in deep sub-micron circuit designStrong Debug skills
- Must be a valuable team player
- Must be having good oral and written communication skills
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.