- Good knowledge of Standard cell layout design
- Good knowledge of CMOS logic
- Experience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable.
- Expertise in using industry-standard tools like cadence Virtuoso, Calibre
- Experience in implementation of ESD layouts, handling Antenna/EM, etc
- Ability to independently debug layout issues
- Good team player
- Positive in SKILL programming or other scripting languages