- Experience in EMIR analysis for multiple modes, including static and dynamic analysis with and without functional vectors.
- Solid expertise in understanding and debugging EMIR issues at the block level.
- Experience in power analysis for design blocks.
- Hands-on experience in floorplanning, place and route, power and clock distribution, and pin placement.
- In-depth knowledge of industry-leading tools such as:
- RedHawk
- Olympus / ICC2
- PrimeTime
- Calibre
- Knowledge of package modeling and package/chip-level analysis is an added advantage.
- Good understanding of physical design verification using Calibre.
- Knowledge of Synthesis and DFT is an added advantage.
- Prior experience with 16nm or finer geometries is preferred.
- Proficient in scripting languages such as Tcl and Perl.
- Must have strong communication skills and be a self-driven individual.
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