- The team will work on synthesis for the complete DDRSS subsystem (1 subsystem - DL1 and 2 or 3 blocks) along with HSC NoC blocks.
- The number of blocks may vary from one project to another.
- One engineer should be capable of handling either 2 critical blocks or 3 non-critical blocks for synthesis activities.
Key Responsibilities
- Perform timing convergence during synthesis.
- Work with the Design team for design updates if logic levels are high.
- Collaborate with the Physical Design (PD) team for floorplan updates if the existing floorplan is not optimal.
- Ensure Power targets (provided by the Power team) and Area targets (provided by the Design team) are achieved.
- Ensure CLP and Functional Verification (FV) reports are clean.
- Review incoming collateral quality using a checklist and ensure all required items are clean before starting synthesis.
- Review outgoing collateral quality using a defined checklist.
- Work with the Design team on porting constraints from previous projects to the current project.
- Support the PD team with constraint updates required to fix timing violations observed during PNR (Place and Route).
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.