Location: Rohini, Delhi

Employment Type: Internship (completion certificate)

Duration: 3 months (Immediate Joiners Preferred)

Work Module: Work from office

We are hiring a VLSI Design Intern to work on RISC-V based SoCs for next-generation edge and AI-vision products. The role provides hands-on exposure across the digital IC design flow, from RTL-to-GDSII development to physical design, while contributing to production-oriented silicon projects.

Key Responsibilities

- RTL design & microarchitecture of RISC-V cores and SoC subsystems in Verilog / SystemVerilog
- Functional verification testbenches, simulation, waveform debug, and coverage closure
- Support logic synthesis, timing analysis, and physical design (floorplan, place & route)
- Read recent research papers & findings; evaluate new techniques low-power methods,



AI accelerators, in-memory computing for our designs
- Document micro-architecture specs and verification results

Required Skills

- Solid digital design and computer architecture fundamentals
- RISC-V ISA knowledge
- Verilog/SystemVerilog
- ASIC/FPGA design flow (RTL Simulation Synthesis)
- Technical research reading and analysis

Preferred Profile

- Open-source EDA Yosys, Icarus Verilog, GTKWave, OpenLane, Sky130 PDK
- Python / TCL scripting • NPU / ISP / DSP exposure GitHub portfolio
- Familiarity with AI tools
- Fast learner with a practical, problem-solving mindset

📌 VLSI Design (Intern) (New Delhi)
🏢 Aniston Technologies
📍 New Delhi