- 15-23 years of experience in ASIC development with a robust background in RTL design, SOC design, Physical Design, System Architecture, Mentor Graphics/Synopsys/Cadence tools.
- Master's degree (M.Tech) or Ph.D./Doctorate in Any Specialization; relevant industrial experience preferred.
- Strong understanding of System Verilog/Verilog programming languages; hands-on experience with DFT techniques like LINT/LTE/LVDS/OVM/UVM etc.
📌 Full Chip RTL Design Architect (Hyderabad)
🏢 Ingenium Digital
📍 Hyderabad
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