We are looking for a skilled and motivated Static Timing Analysis (STA) Engineer with 6 years of experience in VLSI design and timing verification. The candidate will be responsible for timing closure activities across complex SoC/IP designs and will work closely with RTL, Physical Design, DFT, and Signoff teams to ensure high-performance and power-efficient silicon implementation.

Key Responsibilities:

- Perform block-level and full-chip Static Timing Analysis (STA) for ASIC/SoC designs.
- Work on timing closure during synthesis, place-and-route, and signoff stages.
- Develop and maintain STA constraints including SDC creation and validation.
- Collaborate with Physical Design and RTL teams to optimize timing, area, and power.
- Support ECO implementation for timing closure.

Requirements/Qualifications:

- Bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, or related field.




- 3-5 years of hands-on experience in Static Timing Analysis for ASIC/SoC designs.
- Robust understanding of digital design fundamentals and timing concepts.
- Experience with industry-standard STA tools such as PrimeTime, Tempus
- Good knowledge of synthesis and physical design flow.
- Familiarity with scripting languages such as Tcl, Perl, or Python.
- Strong analytical, communication, and teamwork skills.
- Knowledge of signal integrity and noise analysis.

Travel Time:

No Travel

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Senior Engineer II - Design (Chennai)
🏢 Microchip Technology
📍 Chennai