- The ideal candidate will possess a problem-solving mindset, attention to detail and the curiosity to uncover hard to find issues.
KEY RESPONSIBILITIES:
- Collaborate with architects and design engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the recent feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements
REFERRED EXPERIENCE:
- Prior experience in ASIC verification
- Extensive experience in designing and implementing self-checking testbenches, coverage closure techniques and regression management flows
- In depth knowledge of modern verification practices including UVM, Formal Verification and assertion-based test
- Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
- Fluency in Verilog or System Verilog
- Excellent written and verbal communication skills
ACADEMIC CREDENTIAL:
- Bachelor in Electrical/Computer/Software Engineering, Master degree an asset
Comments for Recruiters to be considered during screening profiles:
Must Have:
- write and debug UVM Test
- sub-system integration
- 10 + Years experience needed
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Verification Lead (Hyderabad)
🏢 Proxelera
📍 Hyderabad
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