Job Title: AMS/Macro LEC Engineer - 2-4 Yrs

Location: Hyderabad

No. Of positions: 1

Experience required: 2 to 4 years

Budget: 16-18 LPA

- Conduct hierarchical and block-level equivalence checks
- Analyze and debug LEC mismatches including:
- Port-mismatch issues
- Black-box/undriven signals
- Develop and maintain LEC scripts (TCL/Perl/Python)
- Collaborate with RTL/Circuit team to resolve equivalence failures

Job Deliverables:

- LEC Setup & Execution
- Complete equivalence signoff reports with:
- Zero failing compared points (or justified exceptions)
- Documented waivers (if any)
- Root-cause analysis reports for all non-equivalence issues

Desired Qualification:

- Masters or equivalent

Desired Experience:

- 2-4 years of experience in Synopsys Formality / Cadence Conformal
- Solid RTL knowledge (Verilog/SystemVerilog)
- Expertise in debugging LEC mismatches
- Scripting: TCL (mandatory), Python/Perl

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 AMS/Macro LEC Engineer (Hyderabad)
🏢 Proxelera
📍 Hyderabad