Job Title : Principal Physical Design Architect (SoC Implementation)

Work Experience: 12+ years in Physical Design

Job Role:

We are looking for a highly experienced Principal Physical Design Architect /SME to lead physical implementation solutioning, methodology development, PPA optimization, and implementation planning for complex SoCs.

Key Responsibilities

- Define implementation methodologies for large chips.
- Develop floor planning and partitioning strategies for SoC Level.
- Drive PPA closure approach from Spec to GDS-II.
- Conduct early feasibility and QoR assessments.
- Define clocking, power, and congestion strategies.
- Guide implementation teams globally.
- TSMC Tech Node experience is must
- Experience on AI based EDA tools is required e.g. DSO or Cerberus.
- Review signoff readiness and implementation risks.
- Support customer technical engagements and project estimation.

Candidate Profile:





- 12+ years in Physical Design.
- Multiple tape-outs in advanced nodes (10nm and below).
- Expertise in floor planning, CTS, timing closure, and power optimization.
- Solid knowledge of Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
- Experience with UPF and multi-voltage designs.
- Experience with large SoCs (>100M gates).
- Strong understanding of signoff methodologies.
- Should be able to support and delivery multiple projects simultaneously.
- HBM/HMC memory systems

Good to Have

- 5nm/3nm implementation experience.
- Chiplet-based floor planning.
- 3DIC/Advanced packaging.
- HBM integration experience.
- Automotive or HPC silicon experience.

Please share resume at [email protected]

📌 Principal Physical Design Solution Architect (SoC / AI-Driven EDA) (Hyderabad)
🏢 Capgemini
📍 Hyderabad