Roles and Responsibilities :

- Design verification using SystemVerilog, UVM, and other relevant tools to ensure software meets functional requirements.
- Collaborate with cross-functional teams to identify and resolve issues during the development process.
- Develop test plans, cases, and scripts for complex systems using SystemVerilog's VMM (Virtual Machine Monitor) feature.
- Analyze results from simulations to identify defects and provide recommendations for improvement.

Job Requirements :

- 5-15 years of experience in design verification engineering with expertise in SystemVerilog, UVM, or similar languages.
- Strong understanding of digital logic design principles and ability to apply them to real-world problems.
- Experience working on large-scale projects involving multiple stakeholders across different domains (e.g., hardware/software).
- Proficiency in creating high-quality code that is productive, well-documented, and easy to maintain.

📌 Senior Design Verification Engineer (Hyderabad)
🏢 Einfochips
📍 Hyderabad