Job Description

We are looking for an experienced DFT (Design for Test) Engineer with 7+ years of expertise in ASIC/SoC Design-for-Test implementation and verification. The ideal candidate should have hands-on experience in DFT architecture, scan insertion, ATPG, MBIST, and JTAG, along with robust knowledge of industry-standard EDA tools.

Key Responsibilities

- Develop and implement DFT architecture for complex ASIC/SoC designs.
- Perform scan insertion, scan compression, and ATPG pattern generation.
- Implement and verify MBIST, LBIST, JTAG (IEEE 1149.1), and boundary scan.
- Analyze and improve test coverage while reducing test time and test cost.
- Work closely with RTL, Physical Design, Verification, and Test teams throughout the design cycle.
- Debug DFT-related issues during simulation, synthesis, and silicon bring-up.
- Support post-silicon validation and production testing.

Required Skills

- 7+ years of experience in DFT implementation for ASIC/SoC designs.
- Strong knowledge of Scan, Scan Compression,



ATPG, MBIST, LBIST, and JTAG.
- Experience with Tessent, Synopsys DFT Compiler, TestMAX, or equivalent DFT tools.
- Hands-on experience with Verilog/SystemVerilog.
- Good understanding of digital design fundamentals and RTL design flow.
- Familiarity with synthesis, STA, and physical design constraints related to DFT.
- Experience debugging DFT issues and improving test coverage.
- Strong analytical, problem-solving, and communication skills.

Preferred Skills

- Experience with advanced technology nodes (16nm/7nm/5nm and below).
- Knowledge of IEEE 1500, IEEE 1687 (IJTAG), and advanced DFT methodologies.
- Exposure to Automotive, AI/ML, Networking, or High-Performance Computing SoCs.
- Experience with scripting languages such as Tcl, Perl, or Python.

Interested can share resume at [email protected]

📌 Senior/Lead DFT engineer : Noida/Hyderabad
🏢 incise infotech
📍 Noida