- Design and develop verification environments for complex digital designs using SystemVerilog, UVM, and other relevant tools.
- Collaborate with cross-functional teams to identify requirements and create test plans, cases, and scenarios.
- Develop high-quality code in C to implement verification components such as drivers, monitors, and scoreboards.
- Analyze results from simulation runs to identify defects in the design.
Job Requirements :
- 4-10 years of experience in SOC Verification Engineering with expertise in ARM processors.
- Robust understanding of SystemVerilog programming language and its application in DV environment creation.
- Experience with Universal Verification Methodology (UVM).