Role Overview:
We are seeking a skilled DFT Engineer with strong fundamentals and hands-on experience in test methodologies, debug, and coverage analysis. The ideal candidate will be a collaborative team player who contributes effectively to both technical execution and team growth.
Key Responsibilities
- Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
- Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
- Analyze and resolve issues related to testability, fault coverage, and pattern generation
- Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
- Collaborate with cross-functional teams to ensure smooth DFT integration and issue resolution
- Contribute to continuous improvement of DFT flows, methodologies, and debug efficiency
Required Skills Experience
- Solid understanding of DFT fundamentals including ATPG, scan architecture, and OCC
- Proven hands-on experience in:
- DRC debug
- Coverage debug
- Simulation debug (various modes and scenarios)
- Exposure to SSN, IJTAG, ICL, and PDL frameworks
- Ability to analyze complex issues and provide structured debug solutions
Behavioral Competencies
- Strong team player with a collaborative mindset
- Proactive in learning and sharing knowledge within the team
- Effective communication and coordination skills
- Ownership-driven with focus on quality and timely delivery
Disclaimer : This job posting has been aggregated from external source. Role detailscontentand availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.