{"company":"

About TylSemi, Inc.

The Prospect

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package

Thats what we solve. TylSemi builds the chiplet infrastructure IP the IO, power delivery, and interconnect building blocks that makes AI/HPC systems actually work at scale.

This isnt a nice-to-have. Its the critical path.

Why Now
The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moores Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI theyre all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: Were entering the market at exactly the moment when every major AI/HPC player needs what were building, and their alternatives are disappearing.

Culture & Team: How We Work
No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.

No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

US team: Bay Area preferred, but we hire the best people regardless of location

India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

Were not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. Were building to win.

What We Value

Ownership mindset. Youre not here to execute someone elses roadmap. Youre here to define it.

Bias for action. We move fast. Analysis paralysis doesnt fly here.

Deep technical expertise. This is hard engineering. We need people whove shipped real silicon and debugged real hardware.





Low ego, high standards. We dont care about titles or politics. We care about results.

The Ask

If youre reading this, youre probably comfortable. You have a good job at a stable company with all the benefits.

Were asking you to walk away from that and bet on us.

Heres why you should:

The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what were building.

The team has done this before. Weve built and exited semiconductor companies at scale. This isnt our first rodeo.

The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

The work is consequential. Youre not optimizing someones ad click-through rate. Youre building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if youre the kind of person who wants to take the shot, wed love to talk.

READY TO JOIN

","role":"

Role Overview

We are seeking a highly experienced Principal Engineer STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology nodes. 1

What You ll Do

- Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs.

- Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios.

- Define timing constraints, validate SDCs,



and ensure robust timing methodology execution.

- Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence.

- Analyze and resolve complex timing violations and critical path bottlenecks.

- Support ECO implementation and signoff verification for advanced node tape-outs.

- Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements.

- Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

What We re Looking For

- Bachelor s or Master s degree in Electronics, Electrical Engineering, VLSI, or related field.

- 12+ years of experience in STA and timing signoff for ASIC/SOC programs.

- Solid expertise in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques.

- Hands-on experience with Synopsys PrimeTime, Tempus, StarRC, and related signoff tools.

- Strong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects.

- Experience with advanced technology nodes such as 7nm, 5nm, or below.

- Strong scripting skills in Tcl, Python, Perl, or Shell scripting.

- Excellent technical leadership, debugging, communication, and stakeholder management skills.

Good to Have

- Experience with package-aware timing analysis and chiplet architectures.

- Exposure to AI/ML-driven timing optimization methodologies.

- Familiarity with automotive or high-reliability SOC design standards.

Success in This Role Looks Like

- Successful timing closure and signoff delivery for complex SOC tape-outs.

- Efficient management of timing convergence with minimal ECO impact.

- Improved STA methodology scalability, automation, and execution efficiency.

- Strong technical influence, mentoring contribution, and cross-functional leadership.

"},"

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Principal Engineer STA (Bengaluru)
🏢 tylsemi
📍 Bengaluru