Job Title: Verification Lead - 10+Yrs

Location: Bangalore

No. Of positions: 1

Experience required:10-12 years

The Job Role:

- The preferred candidate will have proven experience verifying complex design blocks at the Subsystem and IP or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing test plans in collaboration with design and verification colleagues in a metric-focused environment.

KEY RESPONSIBILITIES:

- Develop and enhance System Verilog / UVM-based testbenches to verify current features for client, server, graphics, and semi-custom interconnects.
- Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
- Understand TestBench Architecture and develop expertise in TestBench Verification Components.
- Mentor junior engineers.

PREFERRED EXPERIENCE:





- Proficient in IP or Subsystem level ASIC verification
- Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
- Exposure to RTL design, software development, formal verification, or other related domains.
- Experience in UVM TestBench Development for complex designs preferred.
- Industry experience is preferred.

ACADEMIC CREDENTIALS:

- Bachelor s or master s degree in Electronics or Electrical or Computer engineering

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Verification Lead (Bengaluru)
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