- Experience in gate-level power sign-off using PTPX, PrimePower, or equivalent
- Proficiency in RTL/GL power profiling using PowerArtist or similar tools
- Understanding of energetic and leakage power reduction techniques (clock gating, power gating, operand isolation, multi-Vt optimization)
- Ability to analyze power reports, identify hotspots, and drive power closure
Good to Have:
- Familiarity with RTL-to-GDS implementation flow (synthesis, place-and-route, STA)
- Exposure to low-power design methodologies (UPF/CPF, voltage domains)
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