Position: DV Engineer
Location: Kochi
Experience: 3 to 20 Years
- Strong experience in Design Verification using System Verilog, UVM, Assertions (SVA), and Coverage-Driven Verification methodologies.
- Expertise in verification of standard protocols such as AXI, AHB, APB, ACE, CHI, PCIe, USB, Ethernet, MIPI, I2C, SPI, UART, CAN, DDR/LPDDR, HBM, UFS, SD/eMMC, CXL, and SerDes.
- Experience in developing verification plans, UVM testbenches, test cases, regressions, coverage closure, and debugging complex functional issues.
- Robust understanding of Digital Design fundamentals, RTL verification, IP/Sub-System/SoC verification, and simulation/debug tools.
- Knowledge of scripting languages (Python, Perl, Shell/TCL) and experience working closely with design teams to achieve verification sign-off.
Regards,
Karthik
[email protected]
📌 Design and Verification Engineer (Kochi)
🏢 HCLTech
📍 Kochi