Job Description: DFT Engineer

Experience Level: 48 Years
Qualification: B.Tech / B.E / M.Tech / M.E (Electronics, Electrical, VLSI, or related field)

About the Role

We are looking for a skilled DFT (Design for Test) Engineer with robust expertise in Scan implementation to join our team. The ideal candidate will be responsible for driving scan insertion, ATPG pattern generation, and SoC-level DFT activities, ensuring high test coverage and quality sign-off across the design.

Roles & Responsibilities

- Perform Scan Insertion at block and top/SoC level, including scan chain stitching and DFT architecture implementation
- Generate ATPG (Automatic Test Pattern Generation) patterns for stuck-at, transition, and other fault models
- Perform Coverage Analysis and work towards achieving target test coverage goals, identifying and resolving coverage gaps
- Run Unit Delay simulations to validate scan chain functionality and pattern correctness
- Perform Timing Simulations (timing-aware/GLS) to ensure ATPG patterns are functionally and timing accurate on silicon
- Drive SoC-level DFT activities including boundary scan, memory BIST integration, JTAG/TAP controller verification, and top-level DFT connectivity checks
- Debug scan and ATPG failures, working closely with RTL design, verification, and physical design teams to root-cause and resolve issues




- Support DFT sign-off deliverables and documentation for tape-out readiness
- Collaborate with cross-functional teams to ensure DFT requirements are integrated early in the design cycle

Required Skills

- Strong hands-on experience in Scan Insertion (DFT Compiler, Tessent, or similar tools)
- Proficiency in ATPG Pattern Generation and fault grading
- Experience in Coverage Analysis and closure for stuck-at/transition faults
- Strong understanding of Unit Delay and Timing Simulation methodologies
- Working knowledge of SoC-level DFT flows — MBIST, boundary scan, JTAG/TAP
- Good understanding of scan chain architecture, compression techniques, and DFT design rules
- Ability to debug DFT-related issues across RTL, gate-level, and pattern domains

Good to Have

- Exposure to Memory BIST (MBIST) implementation and integration
- Familiarity with DFT tools such as Tessent, DFT Compiler, or Modus
- Scripting skills (Perl/Python/TCL) for DFT flow automation
- Knowledge of low-power DFT considerations (power-aware scan)

Soft Skills

- Strong analytical and debugging mindset
- Good communication skills for cross-functional coordination
- Ability to work independently and manage multiple DFT deliverables under timelines

📌 Dft Verification Engineer (Bengaluru)
🏢 Sasken Silicon Technolgies
📍 Bengaluru