Job Description: RTL Design Engineer

Experience Level: 811 Years
Qualification: B.Tech / B.E / M.Tech / M.E (Electronics, Electrical, VLSI, or related field)

About the Role

We are looking for an experienced RTL Engineer to join our SoC Integration team. The ideal candidate will have strong hands-on expertise in RTL design, verification-adjacent sign-off checks, and full-chip integration flows, and will play a key role in taking SoC designs from RTL through to physical-design-ready sign-off.

Roles & Responsibilities

- Own and drive RTL design and integration for SoC-level blocks and top-level chip integration
- Perform Clock Domain Crossing (CDC) analysis, identify and resolve CDC violations, and ensure robust synchronization schemes across clock domains
- Run and close RTL Lint checks, ensuring adherence to coding guidelines and design best practices
- Develop, review, and maintain SDC (Synopsys Design Constraints) for timing closure across the design
- Work with UPF (Unified Power Format) to define and validate power intent, including power domains, isolation, retention, and level shifters
- Understand and implement chip-level power structures (power gating, multi-voltage domains, always-on logic, etc.)
- Perform Gate Level Simulations (GLS) to validate functional correctness post-synthesis, including timing-aware simulations
- Drive end-to-end SoC design flow: RTL integration, connectivity checks, floorplan awareness, and coordination with DFT, PD, and verification teams




- Debug and resolve integration issues arising from block-level to top-level SoC assembly
- Collaborate cross-functionally with architecture, verification, DFT, and physical design teams to ensure smooth tape-out readiness
- Document design decisions, methodologies, and closure reports for CDC, Lint, SDC, and UPF sign-off

Required Skills

- Strong RTL design and coding skills (Verilog/SystemVerilog)
- Hands-on experience with CDC analysis and closure (tools such as Spyglass CDC, Questa CDC, etc.)
- Proficiency in RTL Lint checking and resolving lint violations (Spyglass Lint, Ascent Lint, etc.)
- Strong understanding of SDC constraints — clock definitions, exceptions, false paths, multicycle paths
- Working knowledge of UPF and low-power design methodology
- Understanding of chip-level power architecture and power intent verification
- Experience running and debugging Gate Level Simulations (GLS)
- Solid grasp of the overall SoC design and integration flow, from RTL to sign-off handoff
- Solid debugging skills and ability to work with cross-functional teams (DV, DFT, PD)

Good to Have

- Exposure to any Low-Speed or High-Speed protocol (e.g., I2C, SPI, UART, USB, PCIe, DDR, MIPI, Ethernet)
- Scripting skills (Perl/Python/TCL) for flow automation
- Experience with formal verification tools

Soft Skills

- Strong analytical and problem-solving ability
- Good communication skills for cross-team coordination
- Ownership mindset with ability to work independently on complex integration tasks

📌 Rtl Design Engineer (Bengaluru)
🏢 Sasken Silicon Technolgies
📍 Bengaluru