Role : Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem):Role :Own end-to-end micro-architecture and ASIC RTL design for complex SoCs or large subsystems, from specification through tapeout and silicon bring-up. This is a deeply hands-on role where solid RTL coding is non-negotiable.What you will do : - Define and own micro-architecture from specs; write high-quality, synthesizable SystemVerilog/Verilog RTL.- Drive block or subsystem integration and close timing, power, and area with PD teams.- Lead design reviews, debug issues, and support silicon bring-up and post-silicon validation.- Partner with DV on test plans, assertions,



and coverage.- Use FPGA/emulation only as a secondary validation aid (not counted toward experience).Must-have :- 8+ years of hands-on ASIC RTL development (FPGA experience does not count toward this requirement).- Multiple production ASIC tapeouts with ownership of SoC or subsystem logic.- Strong RTL coding and micro-architecture ownership in SystemVerilog/Verilog.- Solid experience in clock/reset design, low-power techniques (UPF, retention, isolation).- Working knowledge of AMBA protocols (AXI, ACE, AHB, APB).- Proven collaboration with synthesis, PnR, DFT, ECO, and timing-closure teams.- Direct silicon bring-up experience for owned blocks.Nice to have :- Exposure to coherency, cache/memory subsystems, DDR, PCIe, security or crypto blocks.- SVA for design-level assertions.- Tcl/Python scripting to support hands-on RTL work.What will not count :- FPGA-only or FPGA-heavy roles.- Lint/CDC-only, integration-only, or tool-focused roles without real RTL creation.- Pure management or architect-only roles without recent hands-on RTL work.

📌 Proxelera Senior/Principal ASIC/RTL Design Engineer (Bengaluru)
🏢 Procelera
📍 Bengaluru