Director of Engineering – ASIC Design

Experience: 15+ years of experience in ASIC front-end design and SoC architecture.

Location: Hyderabad

Skills: Verilog, SystemVerilog, microarchitecture, SoC/IP integration, Performance modeling methodologies, power modeling methodologies, ASIC sign-off flows, Lint, CDC/RDC, STA, power analysis, Low-power design, clock gating, power gating, DVFS, Scripting, Python, Perl, TCL, system-level thinking, technical decision-making, communication, mentoring, team-building

Role Summary
We are seeking a highly accomplished Director of Engineering to lead front-end design of advanced SoCs, sub-systems optimized for AI inference, networking, and edge compute workloads. This role requires a robust blend of hands-on technical depth, system-level thinking, and people leadership, driving silicon from concept through RTL, verification, physical design collaboration, and silicon bring-up—while optimizing performance, power, and efficiency.

Key Responsibilities
Microarchitecture Design
Define and implement hardware architectures and micro-architectures optimized for AI inference performance, power efficiency, and scalability. Drive architectural trade-off analysis across compute, memory, interconnect, and I/O subsystems. Collaborate with system and software teams to align hardware architecture with AI workloads and inference use cases.

RTL Design & SoC / IP Integration
Lead development and integration of RTL components using Verilog/SystemVerilog for IPs, sub-systems, and full SoCs. Oversee integration of internal and third-party IPs (ARM, RISC-V, PCIe, UCIe, USB, NoC, memory, AI accelerators). Ensure delivery of QC-clean RTL (Lint, CDC/RDC, UPF compliant) to backend teams.

Functional Verification & Design Quality
Guide and review verification strategy, including testbench architecture,



assertions, and coverage closure. Collaborate with verification teams on simulation-based, formal, and system-level verification. Ensure design robustness through early bug discovery and cross-functional debug.

People & Organizational Leadership
Build, mentor, and lead high-performing teams across, RTL, and integration. Drive performance management, coaching, hiring, and technical career growth. Foster a culture of engineering excellence, accountability, and innovation.

Physical Design Collaboration & Silicon Readiness
Partner closely with physical design teams on synthesis, timing closure, congestion, and power optimization. Provide front-end guidance for floorplan-aware RTL, clocking strategies, and low-power techniques. Support backend sign-off and silicon bring-up, ensuring first-silicon success.

Program Execution & Delivery
Manage schedules, dependencies, and risks across global cross-functional teams. Deliver programs with high quality, predictable execution, and aggressive timelines.

Required Qualifications
Experience
15+ years of experience in ASIC front-end design and SoC architecture. Proven delivery of complex SoCs / AI accelerators in production silicon. Strong background in architecture, RTL, verification, timing, power, and silicon bring-up.

Technical Skills
Verilog / SystemVerilog, microarchitecture SoC/IP integration Performance and power modeling methodologies ASIC sign-off flows: Lint, CDC/RDC, STA, power analysis Low-power design: clock gating, power gating, DVFS Scripting: Python, Perl, TCL

Leadership Skills
Strong system-level thinking and technical decision-making Ability to influence across organizations and geographies Excellent communication with executive and technical stakeholders Proven mentoring and team-building capability

More information about NXP in India... #LI-2734

📌 Director of Engineering – ASIC Design (Secunderabad)
🏢 NXP Semiconductors
📍 Secunderabad