Senior Digital IC Designer

Experience: Not Available to Not Available years

Location: Catania

Skills: Verilog, SystemVerilog, EDA tools, Synopsys Design Compiler, Cadence Genus, Primetime, Synopsys Formality, VCS, QuestaSim, Python, Perl, Tcl

Company Overview
NXP Semiconductors Netherlands B.V. Branch Office Italia

Job Summary
We are seeking an experienced Senior Digital IC Designer to contribute to the development of cutting-edge mixed-signal and digital integrated circuits. This role involves leading complex design tasks from concept to silicon, ensuring high-performance and reliable solutions for NXP's advanced semiconductor products.

Job Responsibilities
• Lead and execute the full digital IC design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, and power analysis.
• Collaborate closely with analog, mixed-signal, and software teams to define interfaces, optimize system performance, and ensure seamless integration.
• Develop and implement innovative digital architectures and design methodologies to meet challenging performance, power, and area targets.
• Perform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation.
• Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
• Mentor junior engineers, provide technical guidance,



and contribute to continuous improvement of design processes and methodologies.
• Generate detailed design documentation, including specifications, test plans, and design reviews.
• Stay abreast of industry trends, emerging technologies, and best practices in digital IC design.

Job Qualifications
• Master's degree or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
• Minimum of 7+ years of experience in digital IC design, with a robust portfolio of successfully completed projects.
• Expertise in Verilog/SystemVerilog for RTL design and verification.
• Proven experience with industry-standard EDA tools for synthesis, STA (e.g., Synopsys Design Compiler, Cadence Genus, Primetime), formal verification (e.g., Synopsys Formality), and simulation (e.g., VCS, QuestaSim).
• Strong understanding of digital design principles, clock domain crossing (CDC) issues, power integrity, and low-power design techniques.
• Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and design flow optimization.
• Familiarity with mixed-signal integration challenges and verification methodologies.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.
• Ability to take initiative, work independently, and lead technical discussions.
More information about NXP in Italy... #LI-7795

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