06 Aug
|
Technogen India Pvt.Ltd
|
Secunderabad
06 Aug
Technogen India Pvt.Ltd
Secunderabad
8+ years of experience in RTL logic design, verification, synthesis, and timing optimization.
Proficient in writing transparent, implementable micro-architecture specifications.
Expertise in writing effective RTL code in Verilog and SoC integration
Valuable understanding of assertions, coverage analysis, RTL synthesis, and timing closure.
Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.
Fluency with scripting languages (e.g., Perl, Python);
Must have gone through at least one tapeout.
Preferred: Silicon bring-up and debug experience
Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA
📌 Application Specific Integrated Circuit Design Engineer Secunderabad
🏢 Technogen India Pvt.Ltd
📍 Secunderabad