Roles & Responsibilities
Hands on experience with layouts of key memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler
context.
Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
Good handle on IR/EM related issues in memory layouts.
Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
Strong knowledge of ultra-deep sub-micron layout design related challenges and valuable understanding of DFM guidelines.
Experience & or solid interest in memory compilers developed.
Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.

Location: Bangalore

Experience: 3+ Years & Above

Qualification: Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics

Number of Positions: 3

📌 Memory Layout Design Engineer Bengaluru
🏢 pozibility technologies
📍 Bengaluru