Senior Design Verification Engineer (Vasanthanagar)

Senior Design Verification Engineer (Vasanthanagar)

06 Aug
|
ACL Digital
|
Vasanthanagar

06 Aug

ACL Digital

Vasanthanagar

Hi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or System C.Experience of working on Functional Verification, So C Verification, EmulationGood in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script,



assembly languageOVM/UVM Methodology knowledge and experienceMust have valuable communication skills and the ability to work in a team environment.Preferably having experience in architecture such as x86 or ARM domain based SOCshaving SOC/IP performance verification background is added plus.Interested can share CV to sharmila.B@About CompanyACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

📌 Senior Design Verification Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar

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