Work Location : Chennai, Bangalore, Cambridge, Malaysia, San Jose

Work Expertise : 5 Years - 15 Years

Desired Profile :

- Bachelor's / Master's degree in engineering from EEE / E&C; with expertise in ASIC STA / SYNTHESIS
- Timing analysis and logic synthesis of digital designs.
- Achieve timing closure and optimize design performance, power and area.
- Perform RTL synthesis using industry-standard tools
- Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL
- Run Static Timing Analysis (STA) and identify timing violations
- Fix setup and hold violations across different corners/modes
- Work on constraints development (SDC creation and validation)
- Analyze timing reports and improve design quality
- Collaborate with RTL, DFT, and Physical Design teams
- Support timing closure during implementation and signoff
- Robust understanding of digital design fundamentals
- Knowledge of synthesis and STA flow
- Familiarity with timing concepts (setup, hold, skew, latency)
- Experience with EDA tools - Genus, Tempus
- Required relevant expertise for Malaysia is 5+ years and 10+ years of relevant expertise for other locations

VISA SPONSORED FOR MALAYSIA

📌 ASIC STA & SYNTHESIS ENGINEER (Chennai)
🏢 Vhunt4U
📍 Chennai