The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities.

Requirements

- 4-8 years of hands-on physical design implementation experience along with APR flow development and PPA analysis
- STA closure at block
- Experience in Advanced process technology nodes (3nm preferred)
- Experience with Cadence layout tools (Innovus, Tempus, etc.)
- Hands on work experience in Physical verification closure (DRC/LVS/Antenna) with Caliber tool
- Experience in closing all the IR issues within the block based on feedback
- Should be strong in fundamentals of digital electronics and microprocessors




- Should have very good analytical skills
- Required soft skills – English language proficiency, Valuable collaboration and interpersonal skills. Good analytical and Problem-solving skills along with strong ownership, commitment and time management.
- Bachelor’s or master's with a relevant education is in the field of electronics and computer architecture

Preferred Skills:

- Strong verbal communication skills
- Cadence PnR tools
- Formal verification experience
- Digital electronics and microprocessors experience

If you are interested in this chance, please click on the Apply Now button to submit your application.

📌 ASIC Physical Design Engineer (Uttar Pradesh)
🏢 Dignity Aspire
📍 Uttar Pradesh