Senior Lead SOC Verification EngineerLNT SLSVE 1660052 LTST-L T Semiconductor Technologies LimitedBengaluru Posted On 27 Jan 2026 End Date 26 Jul 2026 Required Experience 12 - 18 Years Skills Knowledge Posting Location DESIGN VERIFICATION SOC UVM SYSTEM VERILOG - SV Minimum Qualification BACHELOR OF TECHNOLOGY BTECH Position Overview We are looking for a Sr Lead Engineer in SoC Verification to join our team and contribute to the verification of complex SoC designs As a Sr Lead Engineer in SoC Verification you will be responsible for overseeing and executing verification tasks for cutting-edge SoC projects covering RTL-to-Gate-Level Simulation GLS SV UVM based verification setting development functional validation and sign-off This leadership role requires deep expertise in advanced SoC verification methodologies strong technical ownership and the ability to collaborate across architecture design firmware and emulation teams This position contributes directly to first-pass silicon success aligning with the responsibilities and competencies expected in senior verification roles within the organization Key Responsibilities Full-Chip Verification Ownership Lead end-to-end functional and gate-level verification including planning environment development execution debug and sign-off Define and drive verification strategy including testbench architecture assertion strategy scenario modelling regression planning and coverage targets Develop and maintain UVM-based full-chip verification environments reusable components and infrastructure Functional Datapath System and Subsystem Verification Own verification of datapath flows error handling interrupts resets boot flows power modes and SoC integration scenarios Drive end-to-end scenario testing ensuring robustness of SoC functionality and interaction across subsystems Ensure thorough functional code and assertion coverage closure and report progress toward sign-off criteria Testbench Tools Infrastructure Development Build and enhance testbench components verification libraries and infrastructure for multi-million-gate SoCs Support automation development using scripting languages such as Python Perl and TCL Maintain version control and continuous verification practices using GIT CVS and issue tracking tools JIRA Bitbucket Debug Issue Resolution Cross-Functional Leadership Debug complex RTL and GLS failures using industry-standard tools VCS Xcelium Verdi Partner with architecture RTL design PD firmware and validation teams to resolve design and integration issues Provide technical leadership to junior engineers and guide them in methodology debug and best practices Gate-Level Simulation GLS Sign-Off Plan and execute GLS with SDF including test enablement waveform stability validation convergence issues false-path handling and multi-mode timing scenarios Emulation HW SW Co-Verification Collaborate with the emulation team for RTL bring-up on platforms such as Palladium Zebu HAPS Protium Support early software validation boot diagnostics and hardware-software integration Qualifications Bachelor s or Master s degree in Electronics Electrical Engineering Computer Engineering or a closely related discipline 9-12 years of proven experience in SoC verification for complex multi-million-gate designs Deep expertise in industry-standard verification tools such as VCS Xcelium and Questa Strong command of UVM OVM VMM methodologies including testbench architecture constrained-random stimulus generation and coverage-driven verification Advanced proficiency in SystemVerilog SV Assertions Verilog and object-oriented verification frameworks Comprehensive understanding of SoC architecture including interconnects AXI AHB memory subsystems DDR4 LPDDR4 DDR5 LPDDR5 and major peripheral interfaces USB MIPI SDIO Ethernet NFC etc Hands-on experience in Gate-Level Simulation GLS power-aware verification and low-power design validation Strong analytical and debug skills with the ability to diagnose and resolve complex functional integration and performance issues Demonstrated leadership in planning executing and driving verification activities with effective collaboration across architecture design PD firmware and validation teams Proficiency in scripting languages such as Python Perl and TCL to support automation and productivity improvements Excellent communication skills with the ability to articulate technical challenges and influence cross-functional decision-making Preferred Qualifications Experience in formal verification Familiarity with processors boot flows and firmware-driven verification Exposure to hardware software co-verification emulation and rapid-model validation Hands-on knowledge of interfaces such as Ethernet DDR MIPI Security HSM and complex subsystem integration Why Join Us Opportunity to lead full-chip sign-off for a strategic SoC program Work with accomplished R D engineers on next-generation silicon Access to advanced verification and emulation infrastructure Collaborative innovative and quality-focused engineering culture Competitive compensation with strong career growth avenues About Us L T Semiconductor Technologies is a leader in innovative semiconductor solutions committed to pushing the boundaries of technology to create a smarter more connected world We are an equal-opportunity employer We celebrate diversity and are committed to creating an inclusive environment for all employees