Job Details As a Physical Design Engineer you will be responsible for planning designing and validating power delivery networks PDN for System-on-Chip SoC and custom IPs You will leverage Fusion Compiler for PDN implementation and collaborate closely with IP partition owners IR and reliability owners and dedicated IR EM power integrity engineers to understand power requirements and ensure robust PDN solutions Your responsibilities will include but are not limited to Planning and designing PDN for SoCs and custom IPs using Fusion Compiler Performing layout verification of the PDN network and clearing all DRCs Design Rule Checks Collaborating with IP partition owners IR reliability owners and dedicated IR EM power integrity engineers to gather power requirements and implement them in PDN design Ensuring PDN meets performance reliability and area goals Applying best-known methods to create high-quality PDN layouts efficiently The ideal candidate should exhibit the following behavioral traits Strong problem-solving and teamwork skills Effective communication and collaboration across teams Attention to detail and adaptability Ability to work independently and proactively address design challenges Qualifications Minimum qualifications are required to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications BTech in Electrical or Electronics Engineering with 3 years of relevant experience OR MTech in VLSI or related field with 2 years of relevant experience Experience with Fusion Compiler Technical skills required for PD engineers Preferred Qualifications Scripting experience with TCL for automation Relevant expertise in PDN design and implementation Experience in layout design or LV Layout Verification cleanup using Synopsys Fusion Compiler FC or ICC Requirements listed would be obtained through a combination of industry relevant job experience internship experiences and or schoolwork classes research Job Type Intel Contract Employee Shift Shift 1 India Primary Location India Bangalore Additional Locations Business group Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers - from delivering cutting-edge silicon process and packaging technology leadership for the AI era enabling our customers to design leadership products global manufacturing scale and supply chain through the continuous yield improvements to advanced packaging all the way to final test and assembly We ensure our foundry customers products receive our utmost focus in terms of service technology enablement and capacity commitments Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs develops manufactures and assembly test packages the compute devices to improve the lives of every person on Earth Posting Statement All qualified applicants will receive consideration for employment without regard to race color religion religious creed sex national origin ancestry age physical or mental disability medical condition genetic information military and veteran status marital status pregnancy gender gender expression gender identity sexual orientation or any other characteristic protected by local law regulation or ordinance Position of Trust N A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working in office at their assigned Intel site and off-site Job posting details such as work model location or time type are subject to change ADDITIONAL INFORMATION Intel is committed to Responsible Business Alliance RBA compliance and ethical hiring practices We do not charge any fees during our hiring process Candidates should never be required to pay recruitment fees medical examination fees or any other charges as a condition of employment If you are asked to pay any fees during our hiring process please report this immediately to your recruiter