Siemens EDA is a global technology leader in Electronic Design Automation (EDA) software. Our cutting-edge tools empower companies worldwide to develop highly advanced electronic products faster and more cost-effectively. We're pushing the boundaries of technology and physics, enabling our customers to deliver superior products in the increasingly complex world of chip, board, and system design.

As a Hardware Accelerator Designer, you'll be at the forefront of this innovation, collaborating with algorithm architects and a talented team of designers. You'll play a crucial role in deriving architecture and micro-architecture decisions, and implementing and optimizing algorithms to transform them into low-power custom hardware accelerators using high-level synthesis methodologies.

What you'll do:

Develop, test, maintain, and improve design IPs for optimal Power, Performance, and Area (PPA).

Implement functionality in SystemC/C++ and ensure designs meet stringent Latency, Throughput, Area, and Power goals.

Perform comprehensive power, area, and performance trade-off analyses to identify the most efficient solutions.

Leverage High-Level Synthesis (HLS)



to rapidly iterate and evaluate a wide range of possible implementations, narrowing down to the best-suited version.

Drive coverage closure and meet all other sign-off criteria for IPs within a high-level design and verification environment.

Author detailed design documents that clearly articulate your architectural and implementation choices.

What you'll bring:

5-10 years of experience in RTL design (Verilog, SystemVerilog, digital microarchitecture).

A Bachelor's/Masters degree pr PhD Scholars with 6 years of relevant experience are preferred.

Proven experience in breaking down complex digital signal processing algorithms into Micro/RTL architecture, while effectively managing cost and quality trade-offs.

Proficiency in coding with C/C++/Python/Bash.

Experience with High-Level Synthesis (HLS) for ASICs or FPGAs is a significant advantage.

Knowledge of basic processor architecture.

Experience with the full ASIC design cycle (from specification through bring-up) is preferred.

We are Siemens

📌 Lead Engineer (IP Design & Microarchitecture) (Noida)
🏢 Siemens
📍 Noida