Job Description

RTL Design Engineer

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Key Responsibilities

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Analyze architectural specifications and define detailed microarchitecture for digital design blocks.
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Develop synthesizable RTL using Verilog/SystemVerilog for IPs, subsystems, and SoC components.
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Create and maintain design documentation, including microarchitecture specifications, interface definitions, and implementation guidelines.
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Collaborate with architecture teams to evaluate design trade-offs and optimize solutions for performance, power, and area (PPA).
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Perform RTL quality checks, including:
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Lint analysis
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CDC (Clock Domain Crossing) checks
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RDC (Reset Domain Crossing) checks
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Synthesis and design rule compliance reviews
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Support functional verification teams by reviewing test plans, debugging simulation failures, and resolving design issues.
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Work closely with RTL integration teams to ensure proper subsystem and SoC-level integration.
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Support synthesis, timing analysis, and physical design teams in achieving timing and implementation closure.
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Analyze and debug functional, timing, and silicon-related issues during pre-silicon and post-silicon phases.
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Participate in design reviews and ensure compliance with coding standards and development methodologies.
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Contribute to low-power design implementation and power optimization techniques.
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Develop reusable design methodologies, scripts, and automation to improve productivity and design quality.
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Support tapeout activities and provide engineering support through silicon bring-up and validation.
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Required Skills & Experience

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Solid experience in RTL design using Verilog/SystemVerilog.
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Solid understanding of digital design fundamentals, computer architecture, and SoC design concepts.
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Experience in microarchitecture development and RTL implementation.
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Knowledge of AMBA protocols (AXI, AHB, APB) and standard on-chip interconnects.
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Familiarity with lint, CDC, RDC, synthesis, and static timing analysis flows.
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Understanding of low-power design techniques, clock gating, reset architecture, and power intent methodologies.
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Experience with EDA tools for simulation, synthesis, and RTL quality analysis.
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Robust debugging and problem-solving skills.
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Ability to work effectively in cross-functional teams and manage multiple tasks in a fast-paced development setting.
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📌 Rtl Design Engineer Bengaluru
🏢 Mirafra Technologies
📍 Bengaluru