Senior Designer - DFT

Experience: 2 to 4 years

Location: Bangalore, India

Skills: DFT, Digital, STA, VLSI flow, Verilog, Scripting concepts, scan insertion, ATPG, DRC, Coverage Analysis, Pattern Generation, Simulation, Simulation debug, No-timing, Timing, MBIST Verification, DFX feature verification, Pattern generation, JTAG, iJTAG, ICL, PDL, problem-solving, Dft Tools, Tetramax, Testkompress, Modus, IEEE 1149.1, timing analysis, synthesis tools

Job Summary
B.Tech / M.Tech with 2 to 4 years of experience exclusively in DFT. Solid Digital and STA, VLSI flow, Verilog, Scripting concepts. Block or Sub-system level: Hands-on experience to do scan insertion, ATPG DRC, Coverage Analysis, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing. Block or Sub-system level: Hands-on Experience to do MBIST Verification, DFX feature verification, Pattern generation. Working knowledge of JTAG, iJTAG, ICL, PDL etc.



Positive at Communication, self driven VLSI skilled.

Key Responsibilities
Develop And Optimize Scan Chain Structures And Boundary Scan Logic.
Implement Mbist/Lbist Features And Validate Their Functionality.
Collaborate With Verification Teams For Test Coverage Improvement.
Debug Timing And Functional Issues In The Dft Logic.
Generate And Review Atpg Patterns For Fault Coverage.

Skill Requirements
-Experience With Dft Tools Like Tetramax, Testkompress, Or Modus.
-Strong Understanding Of Ieee 1149.1 (Jtag) Standards.
-Proficiency In Timing Analysis And Synthesis Tools.
-Problem-Solving Skills For Debugging Test-Related Issues.

Other Requirements
Optional But Valuable Certifications In Design For Test (Dft) Or Related Areas.

📌 Senior Designer Dft Bengaluru (India)
🏢 HCL Technologies
📍 India